As seen in FIG. 1, during a conventional flip-hip attach process, a microelectronic die 10 including die pads 12 thereon, such as copper bumps, for example, is brought into registration with solder bumps 14 on a package substrate 16 having corresponding land pads (or surface finish layers) 18 supporting the solder bumps, and a solder resist layer 19 supported on a substrate panel 15. A system 11 of interconnects extends through the substrate panel of the substrate and is adapted to allow a connection of the substrate to external circuitry in a well known manner, such as to a printed circuit board (PCB) by way of PCB-side lands of the substrate (not shown). After alignment of respective die pads 12 to corresponding solder bumps 14 of the substrate, the prior art subjects the die-substrate combination to a bonding process including a reflow of the solder bumps. After reflow, the solidified solder forms solder joints 20 (FIGS. 2-5) between the die 10 and substrate 16. Thereafter, an underfill material 23 in liquid form comprising epoxy for example, may be dispensed to flow between the solder joints 20 and a die-attach region 24 of the substrate. The underfill material is typically provided to prevent the solder joints 20 from moving as a result of thermal cycling and electrical shorts during the life of the package. In addition, the underfill material acts as a thermal conductor, mediating the thermal mismatch between die and substrate. A capillary action of the solder joints 20 draws the underfill material into the space between the die and the substrate at the die-attach region. It is not unusual for the liquid underfill material 23 to transgress beyond the die-attach region of the substrate, and in some instances far enough to cover adjacent substrate lands 28, such as those used to attach additional components, such as passive electrical components including capacitors, as shown in FIG. 2.
After the underfill material 23 fills the die-attach region 24, it may be cured to yield a microelectronic package such as packages 25, 35, 45, 55 and 65 of FIGS. 2, 3, 4, 5 and 6, respectively. A typical prior art flip chip package such as package 25/35/45/55/65 includes the substrate 16, the die 10 bonded to the substrate by a bond 26, where the bond includes the solder joints 20 and the underfill material 23 in cured form.
The prior art has attempted to address the problem of underfill transgression beyond the die-attach region and possibly onto the substrate lands such as lands 28 (as shown in FIG. 2) by either: (1) requiring the design of a “keep-out” zone 33 for die-side electrical component placement onto the substrate as shown in FIG. 3; (2) providing a reduced amount of underfill 23 as shown in FIG. 4; and/or (3) providing at least one of trenches 57 and/or barriers 67 in the path of the underfill material 23 flowing out from between the die and the substrate, as seen in FIGS. 5 and 6, respectively. The solution of FIG. 3, however, disadvantageously limits the possibility of reducing package size. The solution of FIG. 4 on the other hand poses reliability issues with respect to the die-substrate bond, as not enough underfill may be provided to bring forth the required benefits of underfill use in the first instance. The solutions of FIGS. 5 and 6 disadvantageously require the provision of additional tools and process flow stages than those in the existing process flow of making the package substrate, raising manufacturing costs and reducing throughput per unit time. In addition, for the barriers 67 shown in FIG. 6, a distance between the barriers and the edge of the die would depend on the actual nature of the barrier material and on how it would be provided. It would be difficult, in general, to put the barrier material within 100-200 microns of the die edge. If the barriers 67 are placed prior to die attach, then physical or chemical interactions between the barrier material and the die attach solder bumps on the substrate would need to be considered during the application of the barrier material and the application of the substrate solder bumps as well as during the chip attach process. As an example, physical masking would be required to physically and chemically protect the bump field during the subsequent application of the barrier material. This physical mask requires a physical space to account for the size of the mask as well as a consideration of possible registration errors of the mask relative to the bump field. As a second example, the barrier material must also be chemically compatible with the chip attach flux and not be degraded during solder reflow. If the barriers 67 placed following chip attach, on the other hand, mechanical interference between the die and the barrier material mask would need to be considered, adding to design complications.
None of the prior art solutions described above and shown in the figures, however, are adequate in providing an effective, reliable and cost-conscious solution to the problem of underfill transgression as described above.
For simplicity and clarity of illustration, elements in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Where considered appropriate, reference numerals have been repeated among the drawings to indicate corresponding or analogous elements.